1. Field of the Invention
This invention relates to a magnetic bubble domain chip and, more particularly, to a chip organization utilizing a unique output decoder and output path arrangement.
2. Description of the Prior Art
In the prior art bubble domain systems, compromises are frequently made with ideal operating conditions. For example, high power requirements are accepted in order to achieve desired access rates. Also, low capacity is accepted to achieve low power consumption. Complexity is frequently endured in order to obtain storage capacity. Other trade-offs are often made. Therefore, it is highly desirable to provide a bubble domain chip organization which maximizes all of these attributes especially by means of multiplexing of storage areas.
The on-chip decoding organization approach has been found to enjoy an advantage of faster access time over other systems such as the serial or major-minor loop organization. The slower access time of known systems is normally attributed to designs that require all blocks of information to be arranged in series, thus requiring the blocks to be rotated, in sequence, to the input/output port. The known systems generally also require data which has been read to be recycled back into the minor loops which lengthens and further complicates the read operation.
In some known organizations, blocks of information are arranged in parallel whereby longer access time and discontinuous data readout can be substantially overcome. However, in the past, the requirement of decoder lines including switches and passive annihilators in the chip designs, as suggested by H. Chang et al, have been plagued with margin overlap of the decoder switch (transfer type) and the passive bubble annihilator. This problem substantially reduces the effectiveness of the existing decoder organization schemes. Moreover, the problems noted supra relative to power, heat and the like are encountered in output decoders too.
The decoder using annihilating type switches proposed in U.S. Pat. No. 4,032,905, Bubble Domain Circuit Organization by Chen, has wide operating margin but requires large operating power. Thus, this organization is not suitable for very large capacity chips. A decoder network using retarding switches has been proposed by Bonyhard et al, "Device Design and System Organization for a Decoder Accessed Magnetic Bubble Memory," AIP Conference Proceedings, No. 18, pt. 1, pp. 100-104. This network has very good operating margin. However, the organization described has all storage registers connected in series and, thus, has very slow clear/write time. Also, the serial system is vulnerable to any circuit defect. This organization again is not suitable for very large capacity chip design.